1. Field of the Invention
The present invention generally relates to inverter circuits and more specifically to a high-speed CMOS (complementary metal oxide semiconductor) inverter circuit.
2. Description of Related
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as MOS (metal-oxide semiconductor) transistor and “source,” “gate,” and “drain” terminals thereof, PMOS (p-channel MOS) transistor, NMOS (n-channel MOS) transistor, and CMOS (complementary MOS). Terms and basic concepts like these are apparent from prior art documents, e.g. text books such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be explained in detail here.
As depicted in FIG. 1, a CMOS inverter 100 receives an input signal and outputs an output signal that is a logical inversion of the input signal. As shown in the call-out box 110, CMOS inverter 100 comprises an NMOS transistor 111 and a PMOS transistor 112. Throughout this disclosure, “VDD” denotes a power supply circuit node. CMOS inverter 100 is well known in prior art and thus not described in detail here.
In CMOS inverter 100 of FIG. 1, the NMOS transistor 111 and the PMOS transistor 112 share a common input and also share a common output. The present invention discloses an alternative scheme that can offer a better performance.